1. Field of the Invention
This application relates to a memory buffer architecture, and more particularly to a buffer architecture with the capability to track master information.
2. Description of the Related Art
Many systems contain random access memory, or RAM, to provide temporary storage of data when a system is powered up. A source within the system, often known as a master, will typically read from the RAM or write to the RAM. To illustrate, a processor in a system may be a master. (Because a master must have control of a bus which connects between the master and the RAM in order to access the RAM, the master is also commonly known as a bus owner or bus master during the time.) Also found in many systems is an interface to the memory, or RAM, known as a RAM, controller. So, for example, in a system using dynamic RAM, or DRAM, a DRAM controller may interface between the master and the DRAM itself.
DRAM controllers, as well as other types of memory controllers, may contain a component or mechanism known as a write buffer. Write buffers permit a master to post writes to the DRAM without incurring DRAM latency penalty. Latency refers to the period of time that one component in a system is waiting for another component. Essentially then, latency is wasted time. In a typical system, a master can send data to the DRAM faster than the DRAM can receive the data from the master. The presence of a write buffer in a DRAM controller, therefore, eliminates the latency problem by permitting the master to send a write to the DRAM without having to wait for the DRAM to actually receive the writes. The write buffer, as intermediary between the master and the DRAM, receives write data from the master, and then forwards the write data to the DRAM, freeing up the master to perform other operations.
Some systems include multiple entities which may perform reads from and writes to DRAM. These systems can thus be said to contain multiple masters. The write buffer in the DRAM controller can, at any given moment, potentially contain write data (to be stored in the DRAM) that came from multiple masters.
When debugging a system that uses multiple masters, identifying the source of DRAM write cycles from the DRAM interface has been difficult or infeasible. A developer who is debugging a system typically attaches a logic analyzer to the DRAM interface, in order to xe2x80x9cseexe2x80x9d what is being written to or read from the DRAM. In the case of writes to DRAM, the write buffer, as opposed to the originating master, appears to be the xe2x80x9csourcexe2x80x9d of write data to the DRAM. The absence of master information during writes to DRAM has frustrated effective system debug. This frustration is particularly acute in systems with many masters.
Briefly, the illustrative system provides a write buffer containing master trace bits which enable a system debugger to determine which master wrote to system memory. The master trace or master contribution bits of the write buffer can be coupled to pins which are externally accessible to a system debugger. For example, in a microcontroller architecture, in which system memory, or DRAM, a DRAM controller, and one or more masters are all part of the microcontroller, the master trace bits are coupled to a plurality of the microcontroller pins. For systems in which the memory, DRAM controller, and masters are discrete components, the master trace bits of the write buffer may instead be coupled to pins on the DRAM controller.
The external pins identify contributing master information during a write buffer write cycle to DRAM. In addition to address tag and byte valid bits, the write buffer includes master trace bits for tracking this master information. When write data intended for the DRAM is sent by a master to the write buffer, a master trace bit is set which associates the data in a data store of the write buffer to the master which provided the data. These master trace bits are each associated with a master which writes to the DRAM.
The master trace bits are coupled to pins which are external, meaning the pins are accessible to a system debugger. So, in a microcontroller architecture, the master trace bits may be coupled to the microcontroller pins themselves. Using a logic analyzer or other debug tool which connects to these external pins, the debugger can then identify which master wrote to DRAM at a particular address. That is, the external pins help to identify which master or bus owner contributed to the current DRAM write cycle. In some cases, more than one master can be a contributor of a particular DRAM write cycle, a condition which is explained in further detail, below. Alternatively, the external pins identify which master (or bus owner) is requesting the current DRAM read cycle. In the case of a read request, only a single master is involved for a particular DRAM read cycle.
In one embodiment, a microcontroller includes a DRAM, a DRAM controller which includes the illustrated write buffer, and three possible bus masters: a central processing unit, or CPU, a peripheral component interconnect, or PCI, bus master, and a direct memory access, or DMA, controller. For this embodiment, three pins are provided to indicate whether the CPU, the PCI bus master, the DMA controller, or a combination of these three masters, has written into a particular location of the write buffer.
In the illustrative embodiment, the trace information of the external pins is available a full clock before the clock edge where the command (either read or write) is driven to the DRAM. This timing parameter facilitates reliable tracking of the master write to DRAM for the system debugger.